The trend in integrated circuits is towards increasing the density of circuit elements in a single chip. This means decreasing the size of individual elements and the spacing betwen individual elements. To provide improved isolation between adjacent elements and contiguous tubs, it is often desirable to provide channel stops, which are regions of relatively high doping, typically under the thick field oxide which overlies passive portions of the chip.
It is characteristic of the manufacture of integrated circuits, and, particularly of high density integrated circuitry, that the simpler the processing, the higher the yield of good chips from a starting wafer of semiconductor material, and so the lower the cost of individual chips.
The present invention in one aspect relates to a process of manufacture of CMOS circuit devices of high density, which requires fewer registrations of masking operations than prior art processes for the manufacture of comparable devices, and in another aspect to the CMOS circuit devices which result from such processing. The fewer registrations result either from the multiple use of the same mask, or from a self-alignment technique that permits the formation of one mask by the use of an earlier formed mask without need of a further alignment.
As is known to workers in the art, the manufacture of integrated circuit devices involves the selective introduction into localized regions of a semiconductive wafer of particular conductivity-type determining impurities, generally known as donor or acceptor ions. The most prevalent technique for such introduction is ion implantation in which chosen ions are accelerated by applied electric fields to penetrate into the interior of the chip. The depth and number of implanted ions are initially controlled by the parameters of the ion beam, and the implantation is localized by the use of apertured masks in the path of the ions, typically layers on the wafer. Later heating is often used to drive the ions deeper.